Digital Counter Circuits

Figure 1.  Circuit Diagram for a 'Ripple' or Asynchronous Counter

The circuit in Figure 1 is that of a 4-bit asynchronous counter, also known as a 'ripple counter'. It consists of 4 J-K flip-flops whose J and K inputs are tied to logic '1'.  This connection causes the output of each J-K flip-flop to toggle every time it gets a clock pulse. By using the output of the previous flip-flop to clock the next flip-flop, a 'rippling' effect is achieved causing the flip-flops to count in binary fashion.

Figure 2.  Circuit Diagram for a Synchronous Counter

The circuit in Figure 2 is that of a 4-bit synchronous counter. It consists of 4 J-K flip-flops, all of which are clocked at the same time, hence the name 'synchronous counter'.  Thus, the toggling of the output of the flip-flops in this counter depends on the states of their J and K inputs. Recall that the J-K flip-flop's output will only toggle when both J and K are 'high'.

The first flip-flop (lease-significant bit) of a synchronous counter has its J and K inputs directly tied to logic '1'.  This causes its output to toggle automatically every time it gets a clock pulse. The second flip-flop's J and K inputs are directly tied to the output of the first flip-flop.  Thus, even if they get clocked at the same time, the second flip-flop will only toggle half the times as the first one. The subsequent flip-flops' J and K inputs are tied to an AND gate whose inputs are tied to the outputs of the last two flip-flops before it. This ensures that each of these flip-flops will toggle at half the rate as the flip-flop before it, even if they are all clocked at the same time.